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Reduced instruction set computer
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#	Item
141	SYSTEM V APPLICATION BINARY INTERFACE MIPS RISC Processor Supplement 3rd Edition Add to Reading List Source URL: refspecs.linux-foundation.org Language: English - Date: 2013-05-29 14:41:04 System V Unix MIPS Technologies Instruction set architectures MIPS architecture Application binary interface UnixWare Santa Cruz Operation Reduced instruction set computing Computer architecture Computing System software
142	SYSTEM V APPLICATION BINARY INTERFACE MIPS RISC Processor Supplement 3rd Edition Add to Reading List Source URL: refspecs.linuxfoundation.org Language: English - Date: 2013-05-29 14:41:04 System V Unix MIPS Technologies Instruction set architectures MIPS architecture Application binary interface UnixWare Santa Cruz Operation Reduced instruction set computing Computer architecture Computing System software
143	Doctoral Studies in Symbolic Computation Symbolic Computation at RISC Symbolic Computation is the subarea of mathematics and computer science which solves problems on symbolic objects Add to Reading List Source URL: www.risc.jku.at Language: English - Date: 2011-12-15 08:55:43 Classes of computers Symbolic computation Reduced instruction set computing Computing Computer science Science Bruno Buchberger SIGSAM Research Institute for Symbolic Computation Computer algebra Hagenberg im Mühlkreis
144	SYSTEM V APPLICATION BINARY INTERFACE MIPS RISC Processor Supplement 3rd Edition Add to Reading List Source URL: refspecs.linuxbase.org Language: English - Date: 2013-05-29 14:41:04 System V Unix MIPS Technologies Instruction set architectures MIPS architecture Application binary interface UnixWare Santa Cruz Operation Reduced instruction set computing Computer architecture Computing System software
145	Processor-Specific ELF Supplement for PA-RISC Including HP and HP-UX Extensions Version 1.43 October 6, 1997 This document is a supplement to the processor-independent definitions of ELF-32 and ELF-64. It Add to Reading List Source URL: refspecs.linuxfoundation.org Language: English - Date: 2013-05-29 14:41:04 Instruction set architectures Assembly languages Reduced instruction set computing Executable and Linkable Format PA-RISC Addition Addressing mode Relocation Ar Computing Computer architecture Software
146	Microsoft PowerPoint - Nintendo 64 Architecture.pptx Add to Reading List Source URL: meseec.ce.rit.edu Language: English - Date: 2014-05-08 16:15:34 R4200 RCP Video game console Sega Saturn MIPS architecture Reduced instruction set computing Nintendo Entertainment System RDRAM 64-bit Computer hardware Humanities Nintendo 64
147	Appears in the 19th IEEE International Symposium on High Performance Computer Architecture (HPCA[removed]Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and x86 Architectures Add to Reading List Source URL: research.cs.wisc.edu Language: English - Date: 2013-02-12 23:17:48 Instruction set architectures Central processing unit Reduced instruction set computing X86 Instruction set DEC Alpha Intel Atom Microarchitecture VAX Computer architecture Computer hardware Computing
148	Software Pipelining for (i=1, i<100, i++) { An alternative method of reorganizing loops Add to Reading List Source URL: homepage.cs.uiowa.edu Language: English - Date: 2006-03-28 11:52:24 Central processing unit Classes of computers Register renaming Software pipelining CPU cache Branch predictor Microarchitecture Reduced instruction set computing Pentium Pro Computer architecture Computer hardware Computer engineering
149	Microprocessors: 1971 to 1976 1971 Intel 4004 2.3 K transistors 12mm2 TI TMC1795 3.2K transistors 30mm2 TI TMS0100 6k transistors 34mm2 Add to Reading List Source URL: icarus.cs.weber.edu Language: English - Date: 2012-12-28 18:12:26 Instruction set architectures Digital electronics Classes of computers Semiconductor devices Microcomputers Microprocessor Reduced instruction set computing Berkeley RISC Transistor Computer hardware Computer architecture Electronic engineering
150	Design and Evaluation of a RISC Processor with a Tomasulo Scheduler Diplomarbeit Lehrstuhl f¨ur Rechnerarchitektur Add to Reading List Source URL: www.kroening.com Language: English - Date: 2014-05-11 10:55:21 Classes of computers Algorithms Tomasulo algorithm DLX Out-of-order execution Central processing unit Reduced instruction set computing MIPS architecture Instruction pipeline Computer architecture Computing Instruction set architectures

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